ELECTROQUIZ
Labels
Basic Electronics
(7)
Communication
(1)
Digital Electronics
(3)
Engineering Math
(2)
Tuesday 30 October 2012
DQ2
Digital Electronics QUIZ 2
Friday 26 October 2012
EQ4
ELECTRONICS QUIZ 4
Thursday 25 October 2012
Basics
Saturday 20 October 2012
EQ3
ELECTRONICS QUIZ 3
Thursday 18 October 2012
EQ2
ELECTRONICS QUIZ 2
MQ2
ENGINEERING MATH QUIZ 2
Thursday 11 October 2012
MQ1
ENGINEERING MATH QUIZ 1
Thursday 4 October 2012
DQ 1
Example Quiz 1
When both inputs of a J-K flip-flop cycle, the output will::
be invalid
change
toggle
not change
One example of the use of an S-R flip-flop is as
:
transition pulse generator
switch debouncer
racer
astable oscillator
An astable multivibrator is a circuit that
:
is free-running and produces a continuous output signal
is free-running
has two stable states
produces a continuous output signal
What is another name for a one-shot
:
bistable
astable
monostable
tristable
What is one disadvantage of an S-R flip-flop?
It has no Enable input.
It has a Race condition
It has no clock input.
It has only a single output.
The truth table for an S-R flip-flop has how many VALID entries
:
3
1
2
4
How many flip-flops are required to make a MOD-32 binary counter
:
3
6
5
45
Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
OR gates and NOT gates
AND gates, OR gates, and NOT gates
AND gates and NOT gates
OR gates only
The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses
:
1000
0000
0010
1111
Which is not characteristic of a shift register?
Serial in/parallel in
Serial in/parallel out
Parallel in/serial out
Parallel in/parallel out
Tuesday 2 October 2012
CQ 1
COMMUNICATION QUIZ 1
Monday 1 October 2012
EQ 1
ELECTRONICS QUIZ 1
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