EQ6

Electronics QUIZ 6

EQ5

Electronics QUIZ 5

DQ3

Digital Electronics QUIZ 3

DQ2

Digital Electronics QUIZ 2

EQ4

ELECTRONICS QUIZ 4

Basics

EQ3

ELECTRONICS QUIZ 3

EQ2

ELECTRONICS QUIZ 2

MQ2

ENGINEERING MATH QUIZ 2

MQ1

ENGINEERING MATH QUIZ 1

DQ 1

1. When both inputs of a J-K flip-flop cycle, the output will::
   be invalid
   change
   toggle
   not change
   
2. One example of the use of an S-R flip-flop is as :
   transition pulse generator
   switch debouncer
   racer
   astable oscillator
3. An astable multivibrator is a circuit that:
   is free-running and produces a continuous output signal
   is free-running
   has two stable states
   produces a continuous output signal
4. What is another name for a one-shot:
   bistable
   astable
   monostable
   tristable
5. What is one disadvantage of an S-R flip-flop?
   It has no Enable input.
    It has a Race condition
   It has no clock input.
   It has only a single output.
6. The truth table for an S-R flip-flop has how many VALID entries:
   3
   1
   2
   4
   
7. How many flip-flops are required to make a MOD-32 binary counter:
   3
   6
   5
   45
8. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
   OR gates and NOT gates
   AND gates, OR gates, and NOT gates
   AND gates and NOT gates
   OR gates only
9. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses:
   1000
   0000
   0010
   1111
   
10. Which is not characteristic of a shift register?
    Serial in/parallel in
    Serial in/parallel out
    Parallel in/serial out
    Parallel in/parallel out

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CQ 1

COMMUNICATION QUIZ 1

EQ 1

ELECTRONICS QUIZ 1